OYO BUTURI Vol.88 No.4 (2019)

Heterogeneous integration of vertical III-V nanowires on Si and their transistor applications

Katsuhiro TOMIOKA1

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si by using a selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. The detailed studies on III-V NW/Si hetero-interfaces showed the possibility for achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs were used for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si hetero-interfaces with fewer misfit dislocations provided us a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could provide new approaches for creating low-power switches as building blocks of future nanoelectronics.

  • 1 Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University
OYO BUTURI Vol.88 No.4 p.245 (2019)