OYO BUTURI
Vol.87
No.12
2018
12
2018128712895
OYO BUTURI Vol.87 No.12 (2018)
Tutorial

Plasma etching process for advanced CMOS and memory device fabrication

Koji ERIGUCHI1, Keiichiro URABE1

This article is about plasma etching processes in transistor fabrication, for current/future CMOS logic and flash memory, i.e. advanced semiconductor devices. In addition to scaling down transistor sizes, their structures have been changed from traditional 2D-planer to 3D complex ones, in recent years. The dynamic evolution has required a reassembly of process designs based on broad views of plasma physics and chemistry. The authors would like to introduce the fundamentals and current technologies of plasma etching, and atomic-scale damages on the semiconductor surface induced by plasma irradiation, for an appropriate process design in future device fabrication.

  • 1 Department of Aeronautics and Astronautics, Graduate School of Engineering, Kyoto University
OYO BUTURI Vol.87 No.12 p.895 (2018)